1. Field of the Invention
The present invention generally relates to accessing memory from a central processing unit (CPU). More particularly, this invention relates to accessing slower Flash or electrically programmable read only memory (EPROM) with a faster CPU using interleaving techniques and memory sub-sections.
2. Description of the Prior Art
FIG. 1 shows a prior art block diagram of a memory 130 being accessed by a central processing unit (CPU) 110 using a memory controller 120. The CPU-Address bus 140 goes into the memory controller 120. The memory controller outputs a wait state control line 150, which goes into the CPU 110. For program execution directly from slow memories such as flash electrically programmed read only memories (EPROMS), the system performance may be limited by the program execution speed. The program execution speed is slowed down by the long access time of memory. The CPU has to “wait” for the memory access to be completed before continuing with the next CPU operation. The wait state control signal from the memory interface controller to the CPU performs this wait function. The memory controller is programmed via programmable read only memory (PROM) to issue wait states of 1, 2, 3, n CPU cycles. The value of n is chosen and programmed to match the slow speed of the chosen memory to the speed of the CPU. This wait state control signal tells the CPU to maintain the CPU-Addr 140 valid for longer periods of time until the wait state signal becomes inactive. Similarly, the memory controller 120 would maintain the Addr 180 valid longer also. For a CPU write operation, the wait state signal tells the CPU to maintain the Data to be written 160 valid for a longer period until the wait state signal becomes inactive. Similarly, for CPU Read operations, the wait state control causes the CPU Addr 140 address to be valid longer and it causes the out-en, output enable line 170 from the memory controller to the memory to remain valid longer.
FIG. 2 shows a timing diagram, which illustrates the workings of the prior art block diagram of FIG. 1. The FIG. 2 diagram shows the CPU clock 220, which paces the operation of the CPU and its system design. The CPU address 230 is the CPU-Addr 140 signal in FIG. 1. It is always kept valid for two CPU clock cycles as shown by the CPU address windows ‘1’, ‘2’, ‘3’, & ‘4’.
The CPU-memory system design shown in FIG. 2 has one wait state added to each CPU cycle. A slower memory could have dictated that two wait state cycles be added to each CPU cycle. The mem address 240, which comes out of the memory controller in FIG. 1, is shown in FIG. 2 to be the same as the CPU address.                U.S. Pat. No. 6,424,680 (Delaruelle, et al.) describes a method of interleaving with low-speed memory. A digital signal is interleaved by delaying samples by an integral number times a unit delay in accordance with a cyclically repeated delay pattern. Select lines of a memory are cyclically activated at a cycle rate equal to unit delay. During the activation of a select line, both data is written and read from the memory. The data written comprises a relevant bit of each sample to be delayed in an integral number of sample groups. Each sample group is associated with one delay pattern cycle. The data read comprises a number of bits, which is equal to the number of bits written. The bits are read in accordance with the delay pattern.        U.S. Pat. No. 6,233,662 (Prince, Jr.) discloses a method and apparatus for interleaving memory across computer memory banks. The method optimizes the flexibility built into some interleavers by configuring an interleaver to improve the throughput of access to computer memory by maximizing the number of banks used for interleaving the memory. The present embodiment improves the process of spreading memory references across multiple memory banks to increase throughput of the memory system by configuring the control registers of an interleaver in a computer system. The present invention configures an interleaver so that it operates across “N” memory banks where “N” is not required to be a power of two.            U.S. Pat. No. 6,026,473 (Cross, et al.) describes a method and apparatus for storing data in a sequentially written memory using an interleaving mechanism. Data values are alternately stored in first and second data hold registers and then output by each data hold register for a time greater than a cycle period of the clock signal. Address values at which the incoming data values are to be written are alternately stored in first and second address hold registers. Data stored in the first data hold register is written to a latch-based memory element in a first memory bank indicated by an address value stored in the first address hold register. Data stored in the second data hold register is written to a latch-based memory element in a second memory bank indicated by an address value stored in the second address hold register.